Semisrael Expo

an event of:
Israeli
Semiconductor
Industry
2016

AVENUE
Airport city

 

Nov. 15, 2016

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Conference Agenda

Participation in all professional tracks is free for semiconductor professionals, and requires early registration and approval.Professional tracks presentations will start after a general assembly session.

Tuesday - November 15, 2016
Event Sponsors:
Mentor-trans12742 ceva trans 15052 snps2016trans Aricent15052 2016  
Cadence 2016 new 15052 AMATMakePossible blue15052 trans globalfoundries2016transparent   
8:00 - 9:00 Registration, Breakfast, Expo Visit, Networking
   
9:00 - 9:05 Welcome Notes
Shuka Zernovizky
CEO, SemIsrael
     
9:05 - 9:25 Keynote: An Industry Survey of Today’s Functional Verification Landscape
Harry Foster

Chief Scientist, Verification, Mentor Graphics
 
9:25 - 9:45 Keynote: Low-Power Embedded Vision in Emerging Autonomous Driving Applications
Yankin Tanurhan

Vice President Engineering, Solutions Group, Synopsys
 
9:45 - 10:05 Keynote: Deep Learning Solutions in Embedded Systems
Ilan Yona
Vice President, GM of Vision BU, CEVA
 
10:05 - 10:25 Keynote: GigaGate SoCs: The Impact of 25 Years of Moore’s Law!
Stephen Roddy
Sr. Group Director, Tensilica Business Unit, Cadence
 
10:25 - 10:45 Keynote: Enabling Value-added Differentiation in Emerging Applications
Subramani Kengeri
Vice President, CMOS Platforms BU, GLOBALFOUNDRIES
 
10:45 - 11:15 Break, Refreshments, Expo Visit, Networking
 
11:15 - 12:35 Track 1:
IP & Cores
Part 1 (click for info)
Track 2:
Front-end Design & Verification
Part 1 (click for info)
Track 3:
Physical Design
Part 1 (click for info)
Track 4:
Post Silicon
Part 1 (click for info)
 
12:35 - 13:10 Break, Refreshments, Expo Visit, Networking
 
13:10 - 14:30 Track 1:
IP & Cores
Part 2 (click for info)
Track 2:
Front-end Design & Verification
Part 2 (click for info)
Track 3:
Physical Design
Part 2 (click for info)
Track 4:
Post Silicon
Part 2 (click for info)
 
14:30 - 16:00 Lucky Draws, Lunch, Expo Visit, Networking
 
15:00 - 17:00 Secure-IC Innovation Workshop (click for info)

 

 Track 1: IP & Cores
Sponsored by Cadence 2016 new 10035
Moderator: Shimon Raviv
Design IP FAE, Cadence
11:15 - 11:35 Reducing CNN Complexity by Over 50x For Real Embedded Applications
Neil Robinson
Product Marketing Director, Tensilica BU, Cadence
11:35 - 11:55  Optimizing Embedded Memory IP for Extreme Market Segments: Very Low Power IoT Applications and Very High Performance Cache Memory Applications
Cameron Fisher
CEO, Mobile Semiconductor
11:55 - 12:15 Automotive DDR DRAM - Moving Into Safety Critical Applications
Michael Chen
Sr. Staff FAE, DesignWare Interface IPs, Synopsys
12:15 - 12:35 The Challenges Posed by In-Chip Conditions to Reaching Working Silicon
Stephen Crosher
CEO, Moortec Semiconductor Ltd
12:35 - 13:10 Break, Refreshments, Expo Visit, Networking
13:10 - 13:30 Sidense 1T-OTP: Competitive Advantage For Smart Connected Devices
Andrew Faulkner
Senior Director of Product Marketing, Sidense Corp.
13:30 - 13:50  New Cellular IoT Use-cases Call For SoC Innovation
Emmanuel Gresset
Business Development Director, Wireless and Wireline Communications BU, CEVA
13:50 - 14:10  Resolving the eXecute-in-Place (XiP) Challenge for IoT and Wearables
Gideon Intrater
CTO, Adesto Technologies
14:10 - 14:30  Is Fixed Point Really Lower Energy/Cost Than Floating Point?
Neil Robinson
Product Marketing Director, Tensilica BU, Cadence

 

 Track 2: Front-end Design & Verification
Sponsored by veriest 2015 100 35
Moderator: Bruce Bergenfeld
Design Technical Leader, Veriest Solutions
11:15 - 11:35 A Paradigm Shift in Verification Methodology
Prakash Narain
President and CEO, Real Intent
11:35 - 11:55  ISDD in Action: The Peregrinations of a Register Along The Design Cycle
Luc Baudoin
Senior Field Applications Engineer, Magillem
11:55 - 12:15 Why You Need CDC Verification for FPGAs?
Eugene Mandel
European Application Engineer - Digital Design & Verification Solution, Mentor Graphics
12:15 - 12:35 FPGA Chip-to-Chip Communication Made Easy
Vlad Feldman
Digital Design Expert, Veriest Solutions
12:35 - 13:10 Break, Refreshments, Expo Visit, Networking
13:10 - 13:30 Using Data Visualization For Functional Verification
Hagai Arbel
CEO, Vtool
13:30 - 13:50  ISO-26262 and Functional Safety of Automotive Chips, an Introduction
Jamil R. Mazzawi
Founder and CEO, Optima Design Automation
13:50 - 14:10  Growing Usage of FPGA in R&D Prototyping
Rohit Joshi
Director, Marketing, Logic Fruit Technologies
14:10 - 14:30  UVM Simulation Acceleration by the Example of Network-on-Chip Design
Krzysztof Szczur
Hardware Verification Product Manager, Aldec

 

 Track 3: Physical Design
Sponsored by mentor100 35
Moderator: Zohar Levy
Calibre Physical Verification AE, Mentor Graphics
11:15 - 11:35 Selecting a Full Custom Design Suite: A Startup Guide
Beny Bar
COO, Newsight Imaging
11:35 - 11:55 Exciting Advances Coming in Physical Verification and DFM
Gil Goldbaum
European Application Engineer, IC Solutions, Mentor Graphics
11:55 - 12:15 Low Power Design Techniques and Challenges
Varnit Jain
Director, Technology, Aricent
12:15 - 12:35 Fast Multi-Physics Optimization and Design Convergence For sub-16nm Designs
Ronen Stilkol
Area Director, Semiconductors Business Unit, ANSYS
12:35 - 13:10 Break, Refreshments, Expo Visit, Networking
13:10 - 13:30 ROM Content Checker
Arie Komarnitzky
Engineering Director, Avnet ASIC Israel (AAI)
13:30 - 13:50 Designing with TSMC Open Innovation Platform (OIP) Ecosystem
Kees Joosse
Director, Business Development, TSMC
13:50 - 14:10 Embedded FPGA for Reconfigurable RTL: Successful Integration in Your SoC
Tony Kozaczuk
Director, Solutions Architecture, Flex Logix
14:10 - 14:30 Addressing Emerging Nodes Challenges With ICCII
Moshe Ashkenazi
Staff Applications Consultant, Synopsys Israel

 

 Track 4: Post Silicon
Sponsored by amkor-logo 100 35
Moderator: Zvika Raviv
11:15 - 11:35  The New SiP: Sensor in Package - Standard Package Platforms For Sensor Fusion and IoT
David Hopkins
Director of Strategic Accounts, Amkor Technology
11:35 - 11:55  From IoT to LTE-A Devices. Significant COT and TTM Reduction With Advantest Wave Scale Solution
Òscar Solano Jimenez
Center of Expertise in RF, ADVANTEST
11:55 - 12:15 2.5D SiP Manufacturing Ecosystem For Volume Production of High Bandwidth Memory (HBM) ASICs
Huzefa Cutlerywala
VP Sales and Technical Solutions, Europe/ASIA, Open-Silicon
12:15 - 12:35 Comprehensive EM Flow to Analyze on-chip and off-chip RF Impairments
Haim Spiegel
EDA RF Specialist, Keysight Technologies
12:35 - 13:10 Break, Refreshments, Expo Visit, Networking
13:10 - 13:30 Packaging Materials and Processes For Big Data Applications
David Hopkins
Director of Strategic Accounts, Amkor Technology
13:30 - 13:50 End to End Measurement Aided Verification of Semiconductor Designs
Tadeusz Asyngier
Applications Engineer, Tektronix
13:50 - 14:10 Specialty Devices – Bridging the Application-to-Fab Gap
Ira Naot
CTO, Etesian Semiconductor
14:10 - 14:30 Designing Unnecessary Cost, Risk, and Cycle Time Out of Advanced ATE PCB's Through Implementation of DFM Practices
Jordan Mackellar
Director of Sales, PTSL-Probe Test Solutions Ltd

 

Participation in all professional tracks is free for semiconductor professionals, and requires early registration and approval.
Professional tracks presentations will start after a general assembly session.

Event Sponsors

mentor 127 42 snps-logo-june2015 150 52 ceva2016logo15052 Aricent15052 2016
GF Logo highres 22531  Cadence 2016 new 15052  AMATMakePossible blue15052