Semisrael Expo

an event of:
Israeli
Semiconductor
Industry
2014

AVENUE
Airport city

 

Nov. 25, 2014

2014conference

Conference Agenda

Participation in all professional tracks is free for semiconductor professionals, and requires early registration and approval.
Professional tracks presentations will start after a general assembly session.

Tuesday - November 25, 2014
Event Sponsors:
mentor 127 42 cevalogo126 44 Synopsys NEW14043 SMIC 126 44  
applied 13044 GF Logo highres 22531 Aricent15054   
8:00 - 9:00 Registration, Refreshments, Expo Visit, Networking
   
9:00 - 9:05 Welcome Notes
Shuka Zernovizky
CEO, SemIsrael
     
9:05 - 9:25 Keynote: IP Platforms: Enabling Innovation, Differentiation - and Success
Sir Hossein Yassaie

CEO, Imagination Technologies
 
9:25 - 9:45 Keynote: Top 5 Trends Likely to Rule Global Semi Industry in 2015
Rich Goldman

VP, Corporate Marketing & Strategic Alliances, Synopsys
 
9:45 - 10:05 Keynote: Getting Ready for FinFET: New Approaches to Improve Quality and Accelerate Yield Ramp
Joseph Sawicki
VP & GM, Design-to-Silicon Division, Mentor Graphics
 
10:05 - 10:25 Keynote: Smart Everything - From the Sand to the Clouds
Mike Rekuc
EVP Worldwide Sales and Marketing, SMIC
 
10:25 - 11:00 Breakfast, Expo Visit, Networking
 
11:00 - 12:20 Track 1:
IP & Cores
Part 1 (click for info)
Track 2:
Front-end Design & Verification
Part 1 (click for info)
Track 3:
Physical Design
Part 1 (click for info)
Track 4:
Post Silicon
Part 1 (click for info)
 
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
 
13:00 - 14:20 Track 1:
IP & Cores
Part 2 (click for info)
Track 2:
Front-end Design & Verification
Part 2 (click for info)
Track 3:
Physical Design
Part 2 (click for info)
Track 4:
Post Silicon
Part 2 (click for info)
 
14:20 - 15:30 Lunch, Lucky Draw, Expo Visit, Networking
 
15:00 - 17:00 Seminar: NTLab - Design House Introduction & Discussion
Organized By: SemIsrael & NTLab

 

 Track 1: IP & Cores (in collaboration with Design & Reuse)
Sponsored by cevalogo10035
Moderator: Hagay Gellis
Technical Marketing Manager, CEVA
11:00 - 11:20 DSP-Based Platforms for the IoT Era
Eran Belaish
Product Marketing Manager, Audio/Voice, CEVA
11:20 - 11:40  IP Prototyping – Needs, Challenges and Solutions
Michael Chen
Staff FAE, DesignWare Interface IPs, Synopsys
11:40 - 12:00 Is The Market Ready To Conquer PCIe 4.0 Challenges?
Yossi Benizri
General Manager, Beyond Electronics
12:00 - 12:20 Designing Resilient on-chip NoC Fabrics to Meet ISO 26262 Automotive Functional Safety Requirements
Xavier van Ruymbeke
Senior Field Application Engineer, Arteris
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
13:00 - 13:20 Leveraging Application Specific Instruction-set Processors in High-Performance Low-Power Embedded Applications
Coby Hanoch
VP Worldwide Sales, Codasip
13:20 - 13:40  The Third Processor – Running Computer Vision on Your SoC
Yair Siegel
Director of Product Marketing, Multimedia, CEVA
13:40 - 14:00  IP Designer: Discover the Power of Application-Specific Processors (ASIPs)
Patrick Verbist
Business Development & FAE, ASIPs & Processors, Synopsys
14:00 - 14:20  One-time Programmable Memory for Smart Connected Applications
Wim van Seters
Director of Sales, Europe and Israel, Sidense Corp.

 

 Track 2: Front-end Design & Verification
Sponsored by Cadence10035
Moderator: Shadi Saba
Director of Program Management, Strategic Initiatives, Cadence
11:00 - 11:20 Expanded RTL Signoff Solutions
Igal Ze'evi
Manager Technical Field Operations, Atrenta
11:20 - 11:40  Advanced Topics in Verification of Clock-domain and Reset Crossings
Oren Katzir
Sr. Technologist, Real Intent
11:40 - 12:00 Ready for IoT: Full System Integration Platform
Vincent Thibaut
VP Application Engineering and Support, MAGILLEM
12:00 - 12:20 Power Aware Clock Domain Crossing Verification
Eugene Mandel
European Application Engineer, Mentor Graphics
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
13:00 - 13:20 Verification for FPGAs - Methodologies and Case Study
Avi Caspi
Design and Verification Leader, Veriest
13:20 - 13:40  Scaling Formal for SoC Verification
Ziyad Hanna
Vice President R&D, Cadence
13:40 - 14:00 New NFC Chip and UHF Tag Chip to Meet EPC-Global ver.2 Standard
Alexey Golovnya
Chief RFID Engineer, NTLab
14:00 - 14:20 Two Methodologies to Reduce Power Consumption in RTL Design
Richard Langridge
Manager, Field Application Engineering, Calypto

 

 Track 3: Physical Design
Sponsored by mentor100 35
Moderator: Uri Krispil
Senior Application Engineer in the MGC Israeli Team, Mentor Graphics
11:00 - 11:20 Tape-Out On Time. Advances in Physical Verification Technologies
Gil Goldbaum
Senior Application Engineer - IC Solutions, Mentor Graphics
11:20 - 11:40  Innovative Clock Building Strategies For Effective Timing Closure of High-Complexity Designs
Ch Uday Kumar
Lead ASIC Design Engineer, Open-Silicon
11:40 - 12:00 Optimizing DSP Core at 16nm Process – Lessons Learned
Idan Grunbaum
VLSI Department Manager, CEVA
12:00 - 12:20 How to Identify and Prevent ESD Issues
Ronen Stilkol
Area Director, ANSYS - Apache
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
13:00 - 13:20 Wideband Transceiver ASICs for Frequencies up to 5Ghz
Alexander Kovalevski
RF Team Leader, NTLab
13:20 - 13:40 Physical Design Considerations for Embedded Memory Integration
Cameron Fisher
CEO, Mobile Semiconductor
13:40 - 14:00 Architecting Low Power - Challenges and Solutions
Zvika Rozenshein
Consultant and Lecturer in the Field of VLSI Computer Architecture and Design, Maple Technologies

 

 Track 4: Post Silicon
Sponsored by amkor-logo 100 35
Moderator: Alberto Burger
VP Operations and Engineering Services, Micon Global
Boaz Shani
D
irector, Business Development, Micon Global
11:00 - 11:20  Amkor Technology Assembly Updates
David Hopkins
Director of Strategic Accounts, Amkor Technology
11:20 - 11:40  Cost Effective IoT Test with Universal Pin ATE
Martin Dresler
Business Development Manager, ADVANTEST
11:40 - 12:00 Design Information Usage in Defect Inspection/Review Flow in Production Fabs For Fast Yield Ramp
Amiad Conley
Technical Marketing Manager, Applied Materials Israel
12:00 - 12:20 Advanced Probe Card Technologies
Joe Mai
Managing Director, JEM Europe
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
13:00 - 13:20 2D and 3D Non Destructive Analysis for Advanced Semiconductor Packages
Kees Revenberg
Managing Director, Maser Engineering
13:20 - 13:40 Amkor Technology Testing Updates
Yoann Robillard
Director Test Business Development, Amkor Technology
13:40 - 14:00 High Speed Communication: Can Test Continue to Keep Up?
Cédric Mayor
VP Marketing, PRESTO ENGINEERING
14:00 - 14:20 Overcoming the Challenges of FPGA Prototyping
Jimmy Chen
VP Marketing, S2C

 

Participation in all professional tracks is free for semiconductor professionals, and requires early registration and approval.
Professional tracks presentations will start after a general assembly session.

Event Sponsors

 

mentor 127 42 cevalogo126 44 Synopsys NEW14043 SMIC 126 44    
applied 13044
 GF Logo highres 22531
 Aricent15054