Semisrael Expo

an event of:
Israeli
Semiconductor
Industry
2015

AVENUE
Airport city

 

Nov. 17, 2015

expo2015 conference

Conference Agenda

Participation in all professional tracks is free for semiconductor professionals, and requires early registration and approval.
Professional tracks presentations will start after a general assembly session.

Tuesday - November 17, 2015
Event Sponsors:
mentor 127 42 cevalogo126 44 Synopsys NEW14043 SMIC 126 44  
Satris150 52 1 applied 13044 GF Logo highres 22531   
8:00 - 9:00 Registration, Refreshments, Expo Visit, Networking
   
9:00 - 9:05 Welcome Notes
Shuka Zernovizky
CEO, SemIsrael
     
9:05 - 9:25 Keynote: Clear Signals Ahead for the Coming Mixed-Signal Revolution
Ravi Subramanian

General Manager, Analog Mixed-Signal BU, Mentor Graphics
 
9:25 - 9:45 Keynote: Prototype in a Day
Eshel Haritan

Vice President, Engineering System Level Solutions, Synopsys
 
9:45 - 10:05 Keynote: Seizing Opportunities in China’s Growing Semiconductor Industry
Paolo Bergamini
Senior Director, Europe General Manager, SMIC
 
10:05 - 10:25 Keynote: Extending Moore's Law with FD-SOI Technology
Gerd Teepe
Design Engineering Director, GLOBALFOUNDRIES
 
10:25 - 11:00 Breakfast, Expo Visit, Networking
 
11:00 - 12:20 Track 1:
IP & Cores
Part 1 (click for info)
Track 2:
Front-end Design & Verification
Part 1 (click for info)
Track 3:
Physical Design
Part 1 (click for info)
Track 4:
Post Silicon
Part 1 (click for info)
 
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
 
13:00 - 14:20 Track 1:
IP & Cores
Part 2 (click for info)
Track 2:
Front-end Design & Verification
Part 2 (click for info)
Track 3:
Physical Design
Part 2 (click for info)
Track 4:
Post Silicon
Part 2 (click for info)
 
14:20 - 15:30 Lucky Draw, Lunch, Expo Visit, Networking

 

 Track 1: IP & Cores
Sponsored by cevalogo10035
Moderator: Svetlana Egorova
Layout Designer, NTLab
11:00 - 11:20 Fastrack to a Smarter IoT
Eran Belaish
Product Marketing Manager, Audio/Voice, CEVA
11:20 - 11:40  FlexNoC Physical: a Physically Aware NoC IP and Associated Development Tools
Xavier van Ruymbeke
Manager, Application Engineering EMEA, Arteris
11:40 - 12:00 Analog IP Porting Automation
Svetlana Egorova
Layout Designer, NTLab
12:00 - 12:20 Processor, DSP and Compiler Creation Made Easy With ASIP Designer
Patrick Verbist
Business Development & FAE, ASIP Tools & Processors, Synopsys
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
13:00 - 13:20 Solutions for Incoming IoT Market
KY Hsieh
Deputy Director, Sales Division, Andes Technology
13:20 - 13:40  Accelerating Machine Learning Deployment with CEVA Deep Neural Network
Liran Bar
Director of Product Marketing, Imaging & Vision, CEVA
13:40 - 14:00  Rapid Development of High-Performance/Low-Power Embedded Processors
Coby Hanoch
VP Worldwide Sales, Codasip
14:00 - 14:20  IPs for Automotive Applications – Needs, Challenges and Solutions
Michael Chen
Sr. Staff FAE, DesignWare Interface IPs, Synopsys

 

 Track 2: Front-end Design & Verification
Sponsored by flexlogix10035
Moderator: Amit Pessach
Director of Verification, Veriest Solutions
11:00 - 11:20 Slash Time-To-Market and Risks: IoT SoC Platforms
Girish Gaikwad
Director, SoC Design, Open-Silicon
11:20 - 11:40  New RTL Sign-off Challenges: Reset Metastability, X-safe Design, and CDC Data Glitches
Oren Katzir
Vice President of Applications Engineering, Real Intent
11:40 - 12:00 A comprehensive Platform For XML Based SoC Integration and Documentation : Re-using All IP Assets and Accelerating Design
Vincent Thibaut
VP, application engineering, Magillem
12:00 - 12:20 Verification IP to Enable High Performance Verification
Eugene Mandel
European Application Engineer - Digital Design & Verification Solution, Mentor Graphics
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
13:00 - 13:20 Verification Infrastructure For Video Applications
Mariana Shenker
Verification Tech Lead, Veriest Solutions
13:20 - 13:40  SoC Development: From Crisis to Opportunity
Rupert Baines
CEO, UltraSoC
13:40 - 14:00  Using Vtool as a Vehicle For Advanced UVM Verification Deployment
Hagai Arbel
CEO, Vtool
14:00 - 14:20  Reconfigurable RTL For Your SoC
Cheng Wang
Co-Founder & VP of Engineering, Flex Logix

 

 Track 3: Physical Design
Sponsored by mentor100 35
Moderator: Zohar Levy
Calibre Physical Verification AE, Mentor Graphics
11:00 - 11:20 Calibre’s Got You Covered for FinFET
Gil Goldbaum
European Application Engineer, IC Solutions, Mentor Graphics
11:20 - 11:40 Introducing AGC on RF - Reasons and Approaches
Andrei Grishkevich
Project CTO, NTLab
11:40 - 12:00 Challenges and Solutions in Back-End Implementation of DSP Cores
Sharon Berlowitz
Physical Design Manager, CEVA
12:00 - 12:20 FinFET and Advanced Technologies SoC Power and Signal Integrity Verification
Ronen Stilkol
Area Director, Apache Business Unit, ANSYS
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
13:00 - 13:20 Power System Design for NanoWatt Sleep Mode Applications
Cameron Fisher
CEO, Mobile Semiconductor
13:20 - 13:40 OMEGA – Analog Expert System - From Schematic to Analog Hard-IP in a Day
Hagay Sakat
VP R&D, Silicon Service
13:40 - 14:00 Designing Low Power Solutions with TSMC's ULP Platforms and FinFET Technologies
Dr. Wen-Chi Chang
Senior Technical Manager, TSMC
14:00 - 14:20 Assembling The Right Pieces of Modern SoC Design: Effective Strategies for Design Collaboration
Manuel Rei
Semiconductor Experience Director, Dassault Systemes

 

 Track 4: Post Silicon
Sponsored by amkor-logo 100 35
Moderator: Joe Mai
Managing Director, JEM Europe
Tom Bresnan
Sales Account Manager, R&D Circuits
11:00 - 11:20  Influence of Test within FC Cu Pillar Packaging Flow
Frederic Beaudoin
Senior Director Sales Strategic Accounts, Amkor Technology
11:20 - 11:40  Massive Multisite – Driver for COT Reduction
Oren Snir
Application Engineer, ADVANTEST
11:40 - 12:00 Real-Time Frequency Domain Imaging Using Immersion Ultrasound (replaced)
Stephen McDonough (replaced by Joe Mai, and Tom Bresnan)
Director of Sales Engineering, OKOS
12:00 - 12:20 eBeam Technology – The Future of Semiconductor Defect Inspection
Ido Holcman
Head of eBeam Technology, Applied Materials
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
13:00 - 13:20 Connecting the Interconnect Gap
David Hopkins
Director of Strategic Accounts, Amkor Technology
13:20 - 13:40 Leveraging Open Architecture, Modular Test Platforms for ATE
Dale Johnson
Customer Technical Services Manager for Marvin Test Solutions, ATSPresto Engineering
13:40 - 14:00 Automated Flow for IC Package Extraction and Performance Assessment with Enablement for IC Package Co-Design
Ilya Zevin
Senior Application Engineer, EDA Integrity Solutions
14:00 - 14:20 2.5D Chip Solution of Networking Die With High Bandwidth Memory (HBM) Over Silicon Interposer
Michael Chen
Senior Technical Manager, GUC

 

Participation in all professional tracks is free for semiconductor professionals, and requires early registration and approval.
Professional tracks presentations will start after a general assembly session.

Event Sponsors

 

mentor 127 42 cevalogo126 44 snps-logo-june2015 150 52 SMIC 126 44    
Satris150 52 1 applied 13044 GF Logo highres 22531