Semisrael Expo

 
to SemIsrael Expo 2014!

an event of:
Israeli
Semiconductor
Industry
2014

AVENUE
Airport city

 

Nov. 25, 2014

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Conference Agenda

Participation in all professional tracks is free for semiconductor professionals, and requires early registration and approval.
Professional tracks presentations will start after a general assembly session.

Tuesday - November 25, 2014
Event Sponsors:
mentor 127 42 cevalogo126 44 spyglass logo12842 SMIC 126 44 applied 13044 marvell logo 15052
8:00 - 9:00 Registration, Refreshments, Expo Visit, Networking
   
9:00 - 9:15 Welcome Notes
Shuka Zernovizky
CEO, SemIsrael
     
9:15 - 9:35 Keynote: Internet of Things (IoT) is a Must
Shmuel Barkan

Joint General Manager Freescale Ltd. and Director of Sales and Marketing for MEA at Freescale Semiconductor
 
9:35 - 9:55 Keynote: Design Methodology and its Impact on the Future of Microelectronics
Ajoy Bose, PhD
Chairman, President and CEO, Atrenta
 
9:55 - 10:15 Keynote: China IC Industries - New Sources for Corporate Customers
Tian-Shen Tang, PhD
Senior Vice President of Design Service, SMIC
 
10:15 - 11:00 Breakfast, Expo Visit, Networking
 
11:00 - 12:20 Track 1:
IP & Cores
Part 1 (click for info)
Track 2:
Front-end Design & Verification
Part 1 (click for info)
Track 3:
Physical Design
Part 1 (click for info)
Track 4:
Post-Silicon
Part 1 (click for info)
 
 
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
 
13:00 - 14:20 Track 1:
IP & Cores
Part 2 (click for info)
Track 2:
Front-end Design & Verification
Part 2 (click for info)
Track 3:
Physical Design
Part 2 (click for info)
Track 4:
Post-Silicon
Part 2 (click for info)
 
 
14:20 - 15:30 Lunch, Lucky Draw, Expo Visit, Networking
 
15:00 - 16:00 Seminar: Enterprise IP Management Infrastructure : Why Should Company Outsource
Organized By: Dr. Gabriele Saucier, CEO, Design And Reuse

 

 Track 1: IP & Cores (in collaboration with Design & Reuse)
Sponsored by cevalogo10035
Moderator: Erez Bar-Niv
CTO, CEVA
11:00 - 11:20 Embedded Vision – Challenges and Solutions
Ilan Yona
Director of Video & Imaging, CEVA
11:20 - 11:40  High Coverage IP Integration Verification Utilizing Formal Technologies
Dr. Raik Brinkmann
President & CEO, OneSpin Solutions
11:40 - 12:00 Antifuse-based High-Density 1T-OTP for Advanced Process Nodes
Wim van Seters
Director of Sales, Europe and Israel, Sidense
12:00 - 12:20 An Objective Quality Validation System for Soft IP
Amit Goldie
Staff Consulting Engineer, Atrenta
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
13:00 - 13:20 High Speed Connectivity With 10G+ SERDES Technology
Michael Chen
Staff FAE DesignWare IPs, Synopsys

13:20 - 13:40  The Role of Vector DSP in Advanced Communications Standards
Michael Boukaya
VP, Chief Architect, CEVA

13:40 - 14:00

Silicon-proven IP cores for Next-generation Security and Wireless SoCs
Pat Rugg
Vice President, Sales and Marketing, The Athena Group

14:00 - 14:20

Why Using Single Root I/O Virtualization Can Help Improve I/O Performance and Reduce Costs?
Michaël Fernandez
Field Application Engineer, PLDA

 

 Track 2: Front-end Design & Verification
Sponsored by jasperlogo100 35
Moderator: Ziyad Hanna
Sr. Vice President of R&D, Jasper Design Automation
11:00 - 11:20 Industrial Strength Behavioral Property Synthesis Technology and Application for Hardware Design Validation
Ziyad Hanna
Sr. Vice President of R&D, Jasper Design Automation
11:20 - 11:40  The Exhilarating Power of ISDD : Integrating Specification, Design and Documentation to Boost Productivity by a Factor of 3
Vincent Thibaut
VP Application Engineer and Support, Magillem
11:40 - 12:00 A Comprehensive Approach to RTL Signoff
Igal Ze'evi
Manager, Technical Field Operations Israel, Atrenta
12:00 - 12:20 Agile Management for Verification Projects
Hagai Arbel
CEO, Veriest Venture
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
13:00 - 13:20 Formal is Normal:  Automatically Refine Your CDC Checking
Dr. Roger B. Hughes
Director of Strategic Accounts, Real Intent
13:20 - 13:40  An Emulation Approach to Challenges in Multimedia Design
David Kaushinsky
Application Engineer, Mentor Graphics
13:40 - 14:00 HW/SW Debug for Embedded Software Debug
Arnold Sher
Sr.  Application Engineer, Synopsys
14:00 - 14:20 PACE and RPM: An Innovative Approach at RTL Level for Predictable Power Budgeting and Power Integrity for ARM IP-based SoC Designs
Vic Kulkarni
Senior Vice President and General Manager, ANSYS-Apache

 

 Track 3: Physical Design
Sponsored by mentor100 35
Moderator: Uri Krispil
Senior Application Engineer in the MGC Israeli Team, Mentor Graphics
11:00 - 11:20 Calibre Physical Verification Platform:  Your Design Deserves Calibre Confidence
Zohar Levy
Application Engineer, Mentor Graphics
11:20 - 11:40  Galaxy Implementation Platform- Low Power Overview
Ziv Leshem
Apps Consultant, Global Technical Services, Synopsys
11:40 - 12:00 Maximizing DSP Performance Using Advanced IP and Design Flow
Ran Snir
VLSI Director, CEVA
12:00 - 12:20 Analog IPs and Their Integration: Multiple RF Paths on Single Die
Andrei Kolotkin
Head of RF Department, NTLab
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking
13:00 - 13:20 3D IC Design Simulation
Ronen Stilkol
Area Director, Israel, ANSYS-Apache
13:20 - 13:40 Success Stories With Low Power and Advanced Design Flow
Jack Wang
General Manger Taiwan office, Senior Sales Director, Brite Semiconductor
13:40 - 14:00 Building Your Own Backend Capability - Practical Guide
Eyal Yatskan & Eli Assoolin
Partners and Managing Directors, Maple Technologies

 

 Track 4: Post Silicon
Sponsored by amkor-logo 100 35
Moderator: Alberto Burger
VP Operations and Engineering Services, Micon
11:00 - 11:20 Amkor Technology Product and Technology Roadmap
David Hopkins
Senior Director - New Business Development Europe and Israel, Amkor Technology

11:20 - 11:40  How to Productize RF Devices Successfully?
Cédric Mayor
VP Technology Innovation & Marketing, Presto Engineering
11:40 - 12:00 An Introduction to Cloud Test, Making Chip Test Available For Everyone
Manabu Kimura

President of Cloud Testing Services Inc.
12:00 - 12:20 Lock-in Thermography Analysis of Reliability Test Rejects
Kees Revenberg
Managing Director and Co-founder, MASER Engineering
12:20 - 13:00 Break, Refreshments, Expo Visit, Networking

13:00 - 13:20

SiP (System in Package) – Taking The Next Step to Higher Integration
Yulia Milshtein
Director of Operations and Business Development, Avnet ASIC Israel (AAI)

13:20 - 13:40

Amkor Test Capabilities and Overview
Isaac Hassine
Test Program Manager, Amkor Technology

13:40 - 14:00

Multiple Accelerated Test Matrix for Reliability Prediction
Joseph B. Bernstein
Professor of Electrical Engineering at Ariel University

14:00 - 14:20

Methodology For Predictive Reliability In Power Electronics
Mathieu Medina
Project Leader, Serma Technologies

 

Participation in all professional tracks is free for semiconductor professionals, and requires early registration and approval.
Professional tracks presentations will start after a general assembly session.

Event Sponsors

 

mentor 127 42 cevalogo126 44 atrenta spyglass 126 44 SMIC 126 44 applied 13044 marvell logo 15052